Digital class-D amplifiers are the trend for audio power amplifiers because of their high efficiency and good sound quality. A conventional digital class-D amplifier consists of a digital PWM modulator and power switches. The digital PWM modulator is usually clocked by a high frequency clock. The dynamic range of this PWM modulator is limited by the phase noise and jitter of the clocks used in the modulator. Therefore, high performance PLL's are essential to achieve high dynamic ranges in digital class-D amplifiers.
The outputs of the PWM modulator typically switch at a frequency of a few hundred kilohertz. This frequency is called the switching frequency. For a high dynamic range, the phase noise of the clock used in the PWM modulator at an offset frequency equal to the switching frequency must be minimized. Hence, new architecture and approaches are needed to achieve the high performance.
Differential control circuits are extensively used in high performance phase locked loops to improve supply and substrate noise. Fully differential charge pumps are often used. In many conventional PLL designs, the voltage controlled oscillator (VCO) itself is usually controlled by a single ended signal, requiring a differential-to-single-ended bias circuit (D2S). However, the bias circuit coming after the loop filter adds intrinsic noise to the VCO, resulting in high jitter. The D2S can be bypassed if the VCO is controlled by a differential signal. This requires that the controlling transistors of the VCO providing the differential signal be complementary in nature.